CZ vs FZ Silicon Wafer: Detailed Comparison and How to Choose

When ordering silicon wafers, the first line on the specification sheet is always the growth method: CZ or FZ. This is not a minor technical detail — it determines the achievable resistivity, mechanical strength, how the wafer behaves in high-temperature steps, and the cost. See what a silicon wafer is if you need the background first.

1. Two crystal growth methods

Czochralski (CZ)

Polycrystalline silicon is melted in a quartz (SiO₂) crucible. A single-crystal seed is dipped into the melt surface, then slowly pulled upward while rotating. Molten silicon solidifies onto the seed and replicates its crystal structure, forming a cylindrical single-crystal ingot. This method produces the majority of the world's wafers.

Float Zone (FZ)

A polycrystalline silicon rod is held vertically. A radio-frequency induction coil surrounds it and melts only a narrow zone, which is held in place by surface tension and the magnetic field — never touching any container. The coil travels along the rod, carrying the molten zone with it; as it passes, impurities are swept toward the far end and single crystal solidifies behind it.

2. The role of oxygen — the core difference

During CZ growth, the quartz crucible is in direct contact with molten silicon above 1400 °C. The quartz erodes slightly and oxygen dissolves into the melt, ultimately entering the crystal. CZ wafers therefore always contain appreciable oxygen, while FZ wafers contain almost none.

Interestingly, oxygen is not purely a harmful impurity. It brings two genuine benefits:

• Mechanical strengthening. Oxygen precipitates in the lattice pin dislocation movement, making CZ wafers more resistant to warping and slip during high-temperature anneals.
• Intrinsic gettering. Oxygen precipitates in the wafer bulk trap heavy metal impurities, drawing them away from the surface region where devices are built. This is a natural cleaning mechanism FZ lacks.

The downside is that oxygen limits the achievable resistivity and can form thermal donors that shift resistivity after heat treatment. For high-voltage power devices or radiation detectors these effects are unacceptable — and that is precisely where FZ becomes necessary.

3. CZ vs FZ comparison table

4. When to choose CZ, when to choose FZ

Choose CZ for digital and analog ICs, MEMS and sensors, general materials and surface research, processes with many high-temperature steps, and anything requiring 8-inch diameters or above. This is the correct default for roughly nine out of ten applications.

Choose FZ when at least one of the following applies:

• High-voltage power devices — thyristors, IGBTs, power diodes — needing a high-resistivity, highly uniform drift region.
• Radiation and particle detectors, where oxygen and impurities shorten carrier diffusion length.
• Substrates for high-frequency applications, where substrate loss must be as low as possible.
• Infrared optics and research demanding the purest silicon, free of oxygen-precipitate interference.
• Experiments sensitive to thermal donors, where resistivity must stay stable through heat treatment.

Digifund supplies CZ-Si wafers at 2", 4", 6" and 8", plus high-purity FZ-Si 4" at 1–100 Ω·cm, double-side polished, 500 ± 25 µm thick. Full specifications are in the Silicon Wafer & Substrate catalog.

5. Grades: Prime, Test, Dummy

After choosing CZ or FZ, the next parameter is grade. All three grades use the same base material but differ in surface defect density, flatness and pre-shipment inspection level.

Choosing the right grade is the single biggest saving lever when buying wafers — details in silicon wafer pricing and its cost drivers.

6. Polishing: SSP vs DSP

SSP (single side polished) gives a mirror finish on one face, leaving the other lapped. The rough face is actually useful: it scatters light so the front side is easy to identify, and it provides extrinsic gettering that traps metal impurities.

DSP (double side polished) gives a mirror finish on both faces. Required when structures are fabricated through the wafer, when light must transmit through it, or when very high overall flatness is needed for double-side-aligned multilayer lithography.

7. Crystal orientation: (100), (110), (111)

Orientation states which crystal plane lies parallel to the wafer surface. It affects directional etch rates, surface state density and how the wafer cleaves.

• (100) — the most common. Low surface state density suits MOSFETs. Anisotropic wet etching produces 54.7° sloped sidewalls, the basis of many MEMS structures.
• (111) — the highest surface atom density. Widely used in surface science, epitaxy and bipolar devices.
• (110) — less common; allows vertical-sidewall etching and offers high hole mobility, useful for certain specialised devices.

Digifund supplies all three orientations ⟨100⟩, ⟨110⟩ and ⟨111⟩ for silicon wafers. If you are unsure, describe the structure you intend to fabricate — the orientation usually follows directly from it.

Frequently asked questions