Contents
1. Four questions before you order
Before consulting any specification table, answer these four questions. They narrow the field faster than any product catalogue:
- What diameter does your equipment accept? This is a hard constraint. Chucks, cassettes, etch chambers and mask aligners all have size limits. A larger wafer cannot be cut down; a smaller one wastes usable area.
- Do you process one face or both? This decides SSP versus DSP, and directly affects cost.
- Does the process include high-temperature steps? If so, substrate mechanical strength matters and you must weigh CZ against FZ.
- What is the output for? Handling practice, tool calibration, or devices for publication? The answer sets the grade — Prime, Test or Dummy.
2. MEMS and sensors
MEMS splits into two branches with quite different substrate requirements.
Bulk micromachining etches deep into the wafer body to form membranes, beams and cavities. Choose silicon with (100) orientation, because anisotropic wet etching in KOH or TMAH stops on the (111) plane, producing highly predictable 54.7° sidewalls. Choose DSP if you need double-side mask alignment — almost always the case for through-wafer etching.
Surface MEMS and thick structures benefit markedly from SOI. The buried oxide (BOX) acts as a natural etch stop, so structural thickness is defined by the manufacturer rather than by etch timing. A common MEMS configuration is a 10 µm device layer over a 2 µm BOX at 6-inch diameter.
3. Photonics and optical communications
Substrate choice depends on whether you need to emit light or merely guide it.
To emit at telecom wavelengths (1310 nm and 1550 nm): use InP. Silicon has an indirect bandgap and emits very poorly; InP has a direct bandgap sitting exactly in the band optical fibre uses. Semi-insulating iron-doped InP is the standard choice for photonic integrated circuits, reducing capacitive crosstalk between components.
To guide and modulate only: use SOI. The refractive index contrast between silicon and buried oxide is large, confining light extremely well in waveguides only a few hundred nanometres across. This underpins the entire silicon photonics industry. Note the BOX must be thick enough that the optical field does not leak into the handle wafer.
4. GaN epitaxy and LEDs
GaN has almost no commercially available native substrate, so most GaN layers are grown heteroepitaxially on a foreign substrate. Selection criteria are lattice mismatch, thermal expansion mismatch and thermal conductivity.
- Sapphire — the most common choice for visible LEDs. Reasonably priced, transparent so light escapes easily, chemically robust. Choose C-plane (0001) with an epi-ready polish. Its weakness is poor thermal conductivity, which caps operating power.
- SiC — several times more thermally conductive than sapphire, with a smaller lattice mismatch to GaN. It is the standard substrate for GaN-on-SiC in RF power amplifiers, where heat removal is decisive.
- AlN — used for UV-C LEDs. Its wide bandgap of roughly 6.2 eV keeps AlN transparent to short-wavelength UV where sapphire begins absorbing. Its small lattice mismatch to aluminium-rich AlGaN also yields markedly better crystal quality.
5. Power electronics and EVs
This is where SiC is displacing silicon fastest. SiC has a wide bandgap and a breakdown field roughly an order of magnitude above silicon, so for the same voltage rating the drift layer can be much thinner and more heavily doped — giving far lower on-resistance and smaller switching losses.
Choose 4H-SiC N-type with nitrogen doping for vertical-conduction devices such as power MOSFETs and Schottky diodes. The 4° off-axis orientation matters because it forces the epitaxial layer to replicate the substrate polytype rather than nucleating a different one. Digifund supplies 4H-SiC N-type at 3", 4" and 6".
If you stay with silicon for high-voltage devices — thyristors, IGBTs — choose FZ over CZ, since the drift region needs high and very uniform resistivity. The full reasoning is in CZ vs FZ silicon wafer.
6. RF, MMIC and 5G
The common requirement across all high-frequency work is a low-loss substrate. A conductive substrate drains energy from transmission lines and destroys circuit quality factor. Semi-insulating substrates are therefore the norm.
- Semi-insulating GaAs — high electron mobility on a low-loss substrate, the classic material for MMICs and low-noise amplifiers.
- SiC HPSI (high-purity semi-insulating) — the substrate for GaN-on-SiC HEMTs in base stations and radar, combining low loss with excellent thermal conductivity.
- RF-SOI — the BOX isolates devices from the handle wafer, sharply cutting loss and crosstalk. It underpins the antenna switch chips in mobile phones.
7. Solar cells and photovoltaics
Photovoltaic research uses a range of substrates depending on the approach. For conventional silicon cells, boron-doped CZ-Si is the industry standard. For very-high-efficiency multi-junction cells, GaAs is the base material thanks to its direct bandgap and high absorption coefficient.
For thin-film, dye-sensitised and perovskite cells, what you need is not a semiconductor wafer but transparent conductive glass. FTO is usually preferred over ITO for processes with high-temperature annealing because FTO is more thermally stable. Digifund supplies ITO glass at 7, 10, 15 and 100 Ω/sq, plus FTO glass at 15 Ω/sq.
8. Teaching laboratories
Teaching labs face the inverse problem of research labs: high wafer consumption but low quality requirements, since the goal is for students to learn handling rather than to produce working devices.
- Handling, tweezer and cassette-loading practice: Dummy wafers. Students will break several in the first week — that is part of learning.
- Lithography, etching and oxidation lab sessions: Test wafers. Good enough to show clear results under a microscope without the expense.
- Final-year projects and theses needing publishable data: Prime wafers, but only the exact quantity for the final run.
Digifund supports small R&D and teaching orders, without the large minimum quantities international manufacturers typically require.
9. Quick reference by application
| Application | Recommended substrate | Key specification |
|---|---|---|
| Bulk MEMS | Si | (100), DSP |
| Thick-structure MEMS | SOI | 10 µm device / 2 µm BOX |
| Silicon photonics | SOI | Thick BOX for confinement |
| Telecom lasers 1310/1550 nm | InP | Semi-insulating (Fe), (100) |
| Visible GaN LED | Sapphire | C-plane (0001), epi-ready |
| UV-C LED | AlN | Single crystal, C-plane |
| Power MOSFET, EV | 4H-SiC | N-type, 4° off-axis |
| High-voltage thyristor, IGBT | FZ-Si | High, uniform resistivity |
| MMIC, LNA | GaAs | Semi-insulating, (100) |
| GaN-on-SiC HEMT | SiC HPSI | Semi-insulating, Prime |
| Mobile RF switch | RF-SOI | 2 µm device / 1 µm BOX |
| Perovskite, DSSC | FTO glass | 15 Ω/sq |
| OLED, touch panel | ITO glass | 7–10 Ω/sq |
| Teaching practice | Si | Test / Dummy |
Frequently asked questions
Which wafer should I use for MEMS research?
For bulk MEMS using anisotropic wet etching, choose (100)-oriented silicon, double-side polished, to get 54.7° sidewalls and allow double-side alignment. For MEMS needing a thick, well-controlled structural layer, choose SOI with roughly a 10 µm device layer over a 2 µm BOX, since the oxide acts as a natural etch stop.
Which substrate suits GaN epitaxy?
Epi-ready C-plane (0001) sapphire is the most common and economical choice for GaN LEDs. Where better thermal conductivity is needed for power or RF devices, use SiC. For short-wavelength UV-C LEDs, single-crystal AlN gives the best epitaxial quality thanks to its small lattice mismatch.
What should a university lab buy?
Split by purpose. Use Dummy wafers for students practising handling and tool operation, Test wafers for calibration and process trials, and Prime only for runs that feed scientific publication. This markedly reduces a lab's annual operating cost.
Which wafer is used for telecom photonics?
For the 1310 and 1550 nm telecom bands, InP is the standard base material because it allows direct-emission lasers and detectors at those wavelengths. Semi-insulating iron-doped InP is typical for photonic integrated circuits. For silicon photonics, use SOI with a BOX thick enough to confine light in the waveguide.
Describe your application, get a specification recommendation
You do not need to know the exact part number. Tell us what you intend to fabricate and what equipment you have — Digifund's technical team will propose a suitable specification set with a quote within 24 business hours.
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